Kibra 380 Analyzer   The Kibra 380 is a stand-alone DDR3 protocol analyzer that provides fast and easy debug of JEDEC bus and timing issues for DDR3.

The Teledyne LeCroy Kibra 380 is a stand-alone DDR3 protocol analyzer that provides comprehensive DDR3 bus and JEDEC timing analysis. Small and portable, the Kibra 380 is controlled over USB using any Windows-based PC and offers state and timing waveform displays to allow fast debugging of DDR3 systems and memory controllers.

Using non-intrusive slot interposer probes, the system provides loss-less capture of address, command and control signals (ADD/CMD/CNTRL). By focusing on state-based capture and excluding the data signals, the Kibra 380 allows quick analysis of DDR3 transactions. With its high impedance probing and specialized trigger logic, this self-contained solution can monitor a fully loaded memory bus and identify over 65 JEDEC bus event and timing violations in real time.

Text-based decoding of commands including all physical address attributes (RA, CA, BA, CS) allow users to see and verify JEDEC ordering violations.

• Fast and Easy DDR3 Debug
  • Self-contained system offers easy connection and setup
  • Impedance matched Interposer style probing
  • No calibration needed!
  • Free trace viewer runs on any PC
• Comprehensive JEDEC Trigger and Capture
  • Detects over 65 JEDEC bus event & timing violations in real time
  • Extended recording time captures 4X the memory events vs typical Logic Analyzer State listing
  • Dedicated trigger output to scope for Read/ Write operations (WE)
• Innovative Displays Focused on Timing Analysis
  • Traditional State and Timing Waveform views
  • Bus metrics are tracked per bank and per DIMM slot
  • Real Time performance displays
• Flexible, Scalable Platform
  • Monitor two slots of quad rank DDR3 DIMMS or SO-DIMMs concurrently
  • Supports registered buffered and unbuffered DIMM types
  • Supports SO-DIMM types (ECC & non-ECC)

The Kibra 380 is the first standalone DDR3 bus analyzer that provides all the essential triggering of a JEDEC pre-processor while simultaneously capturing timing waveforms, decoded state listings, performance, and utilization statistics. Designed specifically to overcome the cost and complexity of monolithic test approaches that rely on logic analyzer platforms, this self-contained solution offers easy connections to system under test.

The Teledyne LeCroy system also features unique, real-time trigger-out to a scope for Read / Write operations (WE). Using this dedicated, low latency SMA trigger out signal, the scope can use the DQ/DQS relationships to distinguish Read / Write operations on the bus.

In addition to timing analysis, the Kibra 380 generates performance metrics that are displayed for read, write, mode register and power down operations. Bus metrics are tracked per bank and per rank to provide insights into overall memory utilization.

Start using the Teledyne LeCroy Kibra 380 immediately without time consuming calibration. Simply enter the memory controller parameters and start recording. The software will automatically load JEDEC timing values for the DIMM type specified. Selectively enable, disable, or customize any of the JEDEC trigger values on-the-fly. Markers are placed at each error event within the Timing view to make it easy to see and verify DDR3 timing.

Small and portable, the Kibra 380 is controlled using any Windows-based PC. It includes the necessary interposer probes capable of monitoring two slots of quad rank DDR3 DIMMs and SO-DIMMs operating to 1600 MT/s. With its unprecedented ease of use, the Kibra 380 solution can replace costly logic analyzer-based debug tools and provide better test coverage at lower overall cost.

DDR is the acronym for Double Data-Rate Synchronous DRAM (SDRAM) and is the terminology used to describe memory used on modern computer systems. It is the successor of PC100/133 SDRAM which was primarily used prior to 1999. DDR was first introduced in 2000 and the primary advantage was its ability to fetch data on both the rising and falling edge of a clock cycle, doubling the data rate for a given clock frequency. For example, in a DDR200 device the data transfer frequency is 200 MHz, but the bus speed is 100 MHz. The DDR memory bus runs at the clock rate of 100 MHz for PC1600, 133 MHz for PC2100, 166 MHz for PC2700 and 200MHz for PC3200. However, each DDR memory module and memory chip run at an effective (data) rate of 200 MHz, 266 MHz, 333 MHz and 400MHz respectively. The computer industry has adopted a practical convention of just referring to the data rate as the DDR DIMM speed. So, PC1600 DIMMs are said to run at 200 MHz, PC2100 DIMMs at 266 MHz and so on.

Like all PC technologies, memory performance and density continue to evolve to meet the demands of faster CPUs. DDR2 was designed to deliver higher overall throughput, the main difference between DDR and DDR2 DRAM is that for DDR2 the memory cells are clocked at 1 quarter the rate of the bus. DDR2 RAM's bus frequency is boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. DDR2 RAM memory also uses a new form factor, a 240 pin DIMM (Dual Inline Memory Module) that is not compatible with the DDR1 standard.

The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3's built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.

Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses "fly-by" routing instead of the "T branches" seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. "Fly-by" takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks - 8 instead of the 4 used by DDR2 - to further speed up the system. More internal banks allow advance prefetch to reduce access latency.

All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy's Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).

Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.

Teledyne LeCroy Kibra 380 DDR3 DIMM Interposers

The Kibra 380 DDR3 DIMM slot interposers are designed for the Kibra 380 system only and are capable of monitoring two slots of DDR3 DIMMs operating to 1600 MT/s.

• Compatible with all standard 204-pin DDR3 UDIMM's, RDIMM's, LRDIMM's at speeds up to 1600 MT/s
• Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
• Integrated cable (18" length) between analyzer and system-under-test
• DDR3 Interposer probes operate non-intrusively and introduce less than 95 ps of latency to the DDR3 signal
• Model numbers: Slot 1 - DDR-AC01-D01-X;   Slot 2 - DDR-AC02-D01-X

The Kibra 380 DDR3 SO-DIMM slot interposers are designed for the Kibra 380 system only and are capable of monitoring two slots of DDR3 SO-DIMMs operating to 1600 MT/s.

• Compatible with all standard 204-pin DDR3 SO-DIMMs at speeds up to 1600 MT/s
• Probes up to 4 ranks using slot 1 interposer or up to 8 ranks when using both slot 1 and slot 2 interposers
• Integrated cable (18" length) between analyzer and system-under-test
• DDR3 SO-DIMM Interposer probes operate non-intrusively and introduce less than 95 ps of latency to the DDR3 signal
• Model numbers: Slot 1 - DDR-AC04-D01-X;   Slot 2 - DDR-AC05-D01-X

Shelf mounting bracket accommodates up to four Kibra 380 or Kibra 480 systems.

• Thumb screw design for tool-less installation
• Model number: ACC-BRKT-013-X